A fully differential synchronous demodulator for AC signals

Abstract

A novel fully differential (FD) demodulator is presented. Using different design strategies, the circuit can be used for processing amplitude-modulated (AM) signals obtained from impedance measurements or coming from modulating sensors with differential outputs where a high common-mode rejection ration (CMRR) and low noise are demanded. The circuit multiplies the AM input signal by a square wave with the same frequency and phase of the carrier of the input signal. This kind of wave is simpler to generate than a sine wave (homodyne detection) and narrow unit-amplitude pulses (synchronous sampling). The proposed circuit is not a perfect floating system, but yields a high CMRR if matched op-amps are used and does not depend on matched resistors. The system has been tested with off-the-shelf amplifiers; at 100 kHz, the CMRR is about 65 dB when fast and wide-bandwidth amplifiers are used. The spectral density of noise voltage obtained is lower than 55 nV/√Hz at 1 kHz; for a bandwidth of 15 Hz, this results in a noise voltage (rms) of 213 nV. Provided the circuit is implemented with low value resistors, the main contribution of noise comes from the noise voltage of the op-amps used to implement the demodulator.